FIG. 1A illustrates the test architecture of a conventional 1149.1 TAP 2. The TAP 2 includes a TAP controller 4, instruction register 6, set of data register including; (1) an internal scan register 8, (2) an in-circuit emulation (ICE) register 10, (3) an in-system programming (ISP) register 12, (4) a boundary scan register 14, and (5) a bypass register 16. Of the data registers, the boundary scan register 14 and bypass register 16 are defined by the IEEE 1149.1 standard. The other shown data registers are not defined by 1149.1, but can exist as data registers within the 1149.1 architecture. The TAP controller 4 responds to the TCK and TMS inputs to coordinate serial communication through either the instruction register 6 from TDI to TDO, or through a selected one of the data registers from TDI to TDO. The TRST input is used to initialize the TAP 2 to a known state. The operation of the TAP 2 is well known.
FIG. 1B illustrates an IC or intellectual property core circuit 18 incorporating the TAP 2 and its TDI, TDO, TMS, TCK, and TRST interface. A core circuit is a complete circuit function that is embedded within an IC, such as a DSP or CPU. FIGS. 1C-1F illustrate the association between each of the data registers of FIG. 1A and the target circuit they connect to and access.
FIG. 2 illustrates the state diagram of the TAP controller 4 of FIG. 1A. The TAP controller is clocked by the TCK input and transitions through the states of FIG. 2 in response to the TMS input. As seen in FIG. 2, the TAP controller state diagram consists of four key state operations, (1) a Reset/Run Test Idle state operation where the TAP controller goes to either enter a reset state, a run test state, or an idle state, (2) a Data or Instruction Scan Select state operation the TAP controller may transition through to select a data register (DR) or instruction register (IR) scan operation, or return to the reset state, (3) a Data Register Scan Protocol state operation where the TAP controller goes when it communicates to a selected data register, and (4) an Instruction Register Scan Protocol state operation where the TAP controller goes when it communicates to the instruction register. The operation of the TAP controller is well known.
FIG. 3 illustrates an example arrangement for connecting multiple TAP domains within an IC 20. The FIG. 3 example and other TAP domain linking arrangement examples are described in application Ser. No. 08/918,872, filed Aug. 26, 1999, now U.S. Pat. No. 6,073,254. Each TAP domain in FIG. 3 is a complete TAP architecture similar to that shown and described in regard to FIG. 1A. While only one IC TAP domain 22 exists in an IC, any number of core TAP domains (1-N) may exist within an IC. As seen in FIG. 3, the IC TAP domain 22 and Core 1-N TAP domains 241-24n are daisy chained between the IC's TDI and TDO pins. All TAP domains are connected to the IC's TMS, TCK, and TRST signals and operate according to the state diagram of FIG. 2. During instruction scan operations, instructions are shifted into each TAP domain instruction register. One drawback of the TAP domain arrangement of FIG. 3 is that it does not comply with the IEEE 1149.1 standard, since, according to the rules of that standard, only the ICs TAP domain should be present between TDI and TDO when the IC is initially powered up. A second drawback of the TAP domain arrangement of FIG. 3 is that it may lead to unnecessarily complex access for testing, in-circuit emulation, and/or in-circuit programming functions associated with ones of the individual TAP domains.
For example, if scan testing is required on circuitry associated with the Core 1 TAP domain, each of the scan frames of the test pattern set developed for testing the Core 1 circuitry must be modified from their original form. The modification involves adding leading and trailing bit fields to each scan frame such that the instruction and data registers of the leading and trailing TAP domains become an integral part of the test pattern set of Core 1. Serial patterns developed for in-circuit emulation and/or in-circuit programming of circuitry associated with the TAP domain of Core 1 must be similarly modified. To overcome these and other drawbacks of the TAP arrangement of FIG. 3, the disclosure as described below is provided.